Integrated circuits (“ICs”) often include metal-oxide-semiconductor (“MOS”) field-effect transistors (“FETs”) to implement circuit functions. MOS FETs generally have a gate electrode separated from a channel region in the semiconductor by a thin layer of gate oxide or other insulating material. Current flow through the channel between drain/source regions according to the gate bias and other factors, such as carrier mobility.
Carrier mobility has been found to be affected by linear stress in the channel region along the major plane of the IC substrate or chip. The carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance. Improving carrier mobility can improve switching speed of a MOS transistor and other characteristics of the transistor. For NMOS transistors, tensile stress in the channel material improves carrier mobility, and for PMOS transistors, compressive stress improves carrier mobility. One mechanism to improve channel mobility is to form a stress-inducing layer over the MOS FET that applies tensile or compressive stress along the plane of the wafer, i.e., along the channel of the MOS FET.
It is desirable to provide consistent transistor characteristic in many circuit applications fabricated in an IC. For example, it might be desirable in some instance to provide matched transistors having essentially equal speed or current draw. In other instances, it is desirable that modeled transistor performance closely match actual transistor performance. Conventional stress-inducing techniques often result in uneven or unequal channel stress, and hence unequal performance or actual performance that is different from modeled performance.